Scan Based Delay Testing

نویسنده

  • Sudheer Vemula
چکیده

Scan Based Delay Testing is used to perform delay testing in the sequential circuits which have the scan capability. In this paper, basics of delay testing and several techniques to perform delay testing for scan based circuits are discussed. The construction of several scan flip-flops along with their advantages and disadvantages is also presented.

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

A Scan-BIST Structure to Test Delay Faults in Sequential Circuits

Delay testing that requires the application of consecutive two-pattern tests is not an easy task in a scan-based environment. This paper proposes a novel approach to the delay fault testing problem in scan-based sequential circuits. This solution is based on the combination of a BIST structure with a scan-based design to apply delay test pairs to the circuit under test.

متن کامل

ATPG and DFT Algorithms for Delay Fault Testing

With ever shrinking geometries, growing metal density and increasing clock rate on chips, delay testing is becoming a necessity in industry to maintain test quality for speed-related failures. The purpose of delay testing is to verify that the circuit operates correctly at the rated speed. However, functional tests for delay defects are usually unacceptable for large scale designs due to the pr...

متن کامل

Scan Design and AC Test

We propose a novel Design for Testability technique to apply two pattern tests for path delay fault testing. Due to stringent timing requirements of deep-submicron VLSI chips, design-for-test schemes have to be tailored for detecting stuck-at as well as delay faults quickly and efficiently. Existing techniques such as enhanced scan add substantial hardware overhead, whereas techniques such as s...

متن کامل

A BIST Structure to Test Delay Faults in a Scan Environment

When stuck-at faults are targeted, scan design reduces the complexity of the test problem. But for delay fault testing, the standard scan structures are not so efficient, because delay fault testing requires the application of dedicated consecutive two-pattern tests. In a standard scan environment, pre-determined two pattern tests cannot be applied to the circuit under test because of the seria...

متن کامل

Scan Cell Design for Enhanced Delay Fault Testability

This paper addresses problems in testing scannable sequential circuits for delay faults. Modifications to improve circuit controllability and observability for the testing of delay faults are implemented efficiently in a scan cell design. A lay-out on a gate array has been designed and evaluated for this scan cell.

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2005